Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to an internal voltage generator which is capable of generating internal voltages having various levels.
In general, a semiconductor memory device including double data rate synchronous DRAM (DDR SDRAM) receives an external voltage, and generates internal voltages having various levels by using the external voltage. Therefore, the semiconductor memory device includes an internal voltage generator provided therein to generate the internal voltages. When the internal voltages generated by the internal voltage generator are used, it may be possible to guarantee more efficient power consumption and more stable circuit operation.
Meanwhile, the internal voltages may be divided into two kinds depending on generation methods.
First, one type of the internal voltages may be generated by down-converting an external voltage. The first type of the internal voltages includes a core voltage and a peripheral voltage. Second, the other type of internal voltages may be generated by pumping an external voltage. The second type of the internal voltages includes a positive high voltage, a substrate bias voltage, and a negative low voltage.
For reference, the positive high voltage and the negative low voltage are voltages which are applied to a word line used for controlling a memory cell. The positive high voltage is used for enabling a word line, and the negative low voltage is used for disabling a word line. The substrate bias voltage is a voltage which is applied to a well or substrate inside a semiconductor memory device, and used for maintaining a contact surface between the well or substrate and an internal circuit in a reverse-bias state, thereby improving circuit characteristics and preventing malfunction. In general, the target voltage level of the substrate bias voltage VBB may be set to approximately −0.8V, and the target voltage level of the negative low voltage VBBW may be set to approximately −0.2V.
FIG. 1 is a block diagram illustrating a conventional internal voltage generator. In the conventional internal voltage generator, a substrate bias voltage VBB and a negative low voltage VBBW are generated by a pumping operation.
Referring to FIG. 1, the internal voltage generator includes a first internal voltage generation unit 110 configured to generate the substrate bias voltage VBB and a second internal voltage generation unit 120 configured to generate the negative low voltage VBBW. The circuit operation and configuration of the first internal generation unit 110 are similar to those of the second internal generation unit 120. Therefore, the following description focuses on the first internal generation unit 110 which generates the substrate bias voltage VBB.
The first internal voltage generation unit 110 includes a first voltage level detection section 111, a first oscillation section 112, and a first pumping section 113. The first voltage level detection section 111 is configured to detect a voltage level of a substrate bias voltage (VBB) terminal, based on a first reference voltage VREF1 corresponding to a target voltage level of the substrate bias voltage VBB, and generate a first detection signal DET1. The first oscillation section 112 is configured to generate a first oscillation signal OSC1 at a predetermined frequency in response to the first detection signal DET1. The first pumping section 113 is configured to generate the substrate bias voltage VBB through a pumping operation in response to the first oscillation signal OSC1.
The first detection signal DET1 may be a signal having a logic high level or a logic low level. When the substrate bias voltage VBB becomes higher than the target voltage level, the first detection signal DET1 becomes a logic high level to enable the first oscillation section 112. When the substrate bias voltage VBB becomes lower than the target voltage level, the first detection signal DET1 becomes a logic low level to disable the first oscillation section 112. Then, the enabled first oscillation section 112 generates a first oscillation signal OSC1 at a predetermined frequency, and the first pumping section 113 lowers the voltage level of the substrate bias voltage VBB toward the target voltage level through a pumping operation in response to the first oscillation signal OSC1.
Similar to the first internal voltage generation unit 110, the second internal voltage generation unit 120 includes a second voltage level detection section 121, a second oscillation section 122, and a pumping section 123. The second internal voltage generation unit 120 generates a negative low voltage VBBW through the above-described pumping operation. In other words, the second voltage level detection section 121 is configured to detect the voltage level of a negative low voltage (VBBW) terminal, based on a second reference voltage VREF2 corresponding to the target voltage level of the negative low voltage VBBW. The second oscillation section 122 is configured to generate an oscillation signal OSC2 at a predetermined frequency depending on the detection result. The second pumping section 123 is configured to generate the negative low voltage VBBW through a pumping operation in response to the oscillation signal OSC2.
Meanwhile, semiconductor memory devices have been designed to perform a variety of operations. Accordingly, various kinds of internal voltages having different target voltage levels are required. Therefore, in order to generate internal voltages other than the substrate bias voltage VBB and the negative low voltage VBBW, various units such as the first and second internal voltage generation units 110 and 120 of FIG. 1 may be additionally needed. In a semiconductor memory device of which the chip size is limited, such additional units may increase the burden in the semiconductor memory device design.